//----------accum.v的开始--------------
module accum(accum,data,ena,clk,rst);
output[7:0] accum;
input[7:0] data;
input ena,clk,rst;
reg[7:0] accum;

always@(posedge clk)
	begin
		if(rst)
			accum <= 8'b0000_0000;		//Reset
		else
			if(ena)							//CPU状态控制器发出load_acc信号
				accum <= data;				//Accumulate
	end
endmodule
//----------accum.v的结束--------------